•  Specification Development
    −  Features definition, performance targets and algorithm development
    −  Technology and package selection for optimal costs (Both NRE and Unit)
         and performance
    −  Dice size estimate for target technology node
    −  Specification document development and review

•  Micro-architecture Development
    −  Data-paths design, control design , and clock and power management
         strategy
    −  Activity summary for power estimation and power budget evaluation
    −  Leverage of in house of IP and from third parties
    −  Micro-architecture documentation and review

•  RTL Coding
    −  Design partitioning and coding and integration of silicon IP

• ASIC Implementation
    −  Pin out design, synthesis and power constraints development and
         synthesis to target technology and library
    −  DFT design, test logic insertion & ATPG to achieve high test coverage

•  Timing and Power Simulation
    −  Timing constraint development and timing and power simulation over
         supply voltage and process corners based on estimated parasitics
    −  Review and release net list for back end ASIC implementation