•  Verification Environment Development
    −  BFM definition and development
    −  Automatic checkers and monitors definition and development
    −  Leverage in house verification IP and from external sources
    −  Integration of Verification environment with DUT

•  Simulation Test Case Development
    −  Test plans development and review
    −  Test case coding and design debug

•  RTL Verification Evaluation
    −  Code Coverage
    −  Addition of cases to golden RTL
    −  Review and Release RTL to backend ASIC Design

• Gate Level Simulation
    −  Re-run test cases on pre-layout and post layout back annotated net lists
    −  Review and Release design for Fabrication