•  ASIC to FPGA Conversion Planning
    −  Decide on all the IP blocks required for FPGA conversion – such as BRAMs,
         Serdes and other cores based on the FPGA RTL design
    −  Select package and technology for optimal costs (NRE and UNIT) and
         performance

•  RTL Development
    −  Modify the FPGA RTL based on the target technology library and IP

•  RTL Verification
    −  Set up verification environment and code test cases to verify RTL
    −  Run code coverage and add cases till golden RTL

•  ASIC Implementation
    −  Pin out design, Synthesis constraints, power constraints and synthesis to
         target technology and library
    −  DFT Design, test logic insertion & ATPG

•  Timing and Power
    −  Timing and power constraint development , and timing and power
         simulation over supply voltages and process corners based on estimated
         parasitics
    −  Review and Release net list for back end ASIC implementation

•  Back End and Tape Out
    −  Whizz Silicon will work with back end customer chosen design services
         vendor or its partners to tape out the devices to target foundry